The present invention relates to a technology of scheduling multiple hardware threads, for example, in a multi-thread processor having the multiple hardware threads.
A hardware multi-thread technology for enhancing a throughput of a processor has been proposed. A processor that supports hardware multi-threads (hereinafter called a multi-thread processor) has multiple hardware threads that generate mutually independent instruction streams, respectively, and performs an arithmetic processing while switching an arithmetic operation circuit for executing an instruction with a pipeline to process an instruction stream generated by a hardware thread.
In the multi-thread processor, scheduling of the multiple hardware threads is required. As a technique of the scheduling, the round robin system and the priority system are known. In the round robin system, the hardware threads put in a queue are selected in turn for every fixed time and are executed. Therefore, in the round robin system, a thread in the queue is assigned fairly to a CPU for every fixed time, and is executed. Moreover, the priority system performs a hardware thread in order of the priority of the hardware thread. Specifically, in the priority system, a hardware thread of each priority is queued to a queue provided for each priority, and the hardware thread is selected sequentially from the queue of a high priority and is assigned to the CPU to be executed.
However, as a problem common to the round robin system and the priority system, there is a problem that it is impossible to set an execution time of the hardware thread flexibly while ensuring a minimum execution time of the hardware thread. For example, in the round robin system, when there are many hardware threads, there is a problem that the execution time of each thread decreases equally and a sufficient execution time cannot be assigned to a high priority hardware thread. Moreover, in the priority system, there is a problem that when processings of the high priority hardware threads continue, a low priority hardware thread cannot be processed.
A technique for addressing this problem is disclosed in Japanese Unexamined Patent Application Publication No. 2010-86128. This technique divides one circulation period of scheduling into a first execution period and a second execution period, specifies execution of one or more hardware threads that are selected fixedly among multiple hardware threads of the multi-thread processor in the first execution period, and specifies execution of an arbitrary hardware thread in the second execution period. The scheduler in the multi-thread processor performs the scheduling by repeating such a circulation period.
To the multi-thread processor to which the technique is applied, for example, in the first execution period, a hardware thread whose minimum execution time is intended to be secured is defined, and in the second execution period, an arbitrary hardware thread is defined according to a processing situation at that time. By doing this, the hardware thread to be executed in the first execution period is executed irrespective of the priorities of other hardware threads. Moreover, an arbitrary hardware thread can be executed in the second execution period.